As industry continuously miniaturizes circuits by compressing passive and active electrical components into smaller areas, thermal management difficulties are exacerbated and additional stress is placed on device interconnects. For circuitry comprised of monolayer graphene, multilayer graphene, graphene microstructures, or graphene nanostructures, especially flexible circuitry, there is a current need for more robust device interconnects that can withstand a variety of shapes and contours while reducing or eliminating junction resistance.